Research

In this study, we propose the CFPE (compact and flexible processing element) architecture as a vision chip architecture that enables various visual processings on the same architecture and combines high speed and the high accumulation. In the proposed architecture, the processing element of each pixel is simplified based on the following 3 design policies, and the integration of the vision chip is improved; 1) pixel local operation by recurrent processing, 2) circuit sharing of pixel local operation and summation operation, and 3) simplification of circuit element.

In the case of the prototype 256 x 256 pixel vision chip, the execution time is 140 us to calculate the center of gravity and 220 microsecond to calculate all the 25 HLAC features. This implies that our developed vision chip enables high-speed image feature extraction in the order of sub-milliseconds.

A 16 x 16 pixel prototype vision chip based on the CFPE architecture is integrated on a 2.5 mm x 2.0 mm chip using a 0.35 um CMOS process. Since the pixel is compactly designed in an area of 33.0 um x 33.0 um, 100,000 pixels can be integrated in a chip area of 1 cm x 1 cm.