Research

In this study, we propose a new vision chip architecture specialized for target tracking and recognition, and developed a prototype vision chip. Both higher order correlation features

and moment features extraction algorithms are implemented in the proposed architecture in order to achieve high-speed image processing and enhanced pixel integration. The prototype chip using 0.35um CMOS DLP/TLM(3LM) process has been developed, with 64x64 pixels integrated on a 5mmx5mm chip. The area per pixel is 44umx48um, hence, 47,000 pixels can be integrated in the chip area of 1cmx1cm. The maximum power consumption of the prototype chip is approximately 400mA.

The object-counting experiment was performed, in which, the objects are arranged on a high-speed rotation drum, and the number of objects are recognized and counted using the HLAC feature.